Digital Logic Cancellation Block for a Cascade Feed-Forward Sigma-Delta Analog-to-Digital Converter

This paper presents the characterization and synthesis results for a hardware implementation of a reconfigurable digital logic cancellation circuit auxiliary for multi-mode Σ∆ modulator that is capable to perform the analog-to-digital conversion for GSM, CDMA and WLAN standards. The Σ∆ modulator reconfigures its mash topology and building blocks in order to adapt the performance to the diverse standard specifications. The necessary integration and cancellation at three modulators output for baseband signal processing was designed in high level Matlab/Simulink and coded with VHDL for synthesis intended to prototyping in CMOS process.